Superconductor analog to digital converter

ABSTRACT

Superconductor analog-to-digital converters (ADC) offer high sensitivity and large dynamic range. One approach to increasing the dynamic range further is with a subranging architecture, whereby the output of a coarse ADC is converted back to analog and subtracted from the input signal, and the residue signal fed to a fine ADC for generation of additional significant bits. This also requires a high-gain broadband linear amplifier, which is not generally available within superconductor technology. In a preferred embodiment, a distributed digital fluxon amplifier is presented, which also integrates the functions of integration, filtering, and flux subtraction. A subranging ADC design provides two ADCs connected with the fluxon amplifier and subtractor circuitry that would provide a dynamic range extension by about 30-35 dB.

REFERENCE TO RELATED APPLICATIONS

The present application is a Continuation of U.S. patent applicationSer. No. 14/522,842, filed Oct. 24, 2014, now U.S. Pat. No. 9,312,878,issued Apr. 12, 2016, which is a Continuation of U.S. patent applicationSer. No. 13/482,226, filed May 29, 2012, now U.S. Pat. No. 8,872,690,issued Oct. 28, 2014, which is a Continuation of U.S. patent applicationSer. No. 12/542,585, filed Aug. 17, 2009, now U.S. Pat. No. 8,188,901,issued May 29, 2012, which claims benefit of priority from U.S.Provisional Patent Application No. 61/089,489, filed Aug. 15, 2008, theentirety of which is expressly incorporated herein by reference.

STATEMENT OF GOVERNMENT RIGHTS

This invention was made with government support under contract #N00014-06-1-0041 awarded by The U.S. Navy. The government has certainrights in the invention.

FIELD OF THE INVENTION

The present invention relates to the field of radio frequencyanalog-to-digital converters and methods, and more particularly toanalog-to-digital converters with very large dynamic range.

BACKGROUND OF THE INVENTION

The inexorable pursuit of higher performance analog-to-digitalconverters (ADCs) is fundamental to progress in direct digitalradio-frequency receivers and related instrumentation. Cryogenicsuperconducting ADCs enable ultrafast switching speed, low power,natural quantization of magnetic flux, quantum accuracy, and low noise,which in turn enable fast and accurate data conversion between theanalog and digital domains. Based on rapid single-flux quantum (RSFQ)logic, these integrated circuits are capable of achieving performancelevels unattainable by any other technology, as reviewed in O. A.Mukhanov, D. Gupta, A. M. Kadin, and V. K. Semenov, “SuperconductorAnalog-to-Digital Converters,” Proceedings of the IEEE, vol. 92, pp.1564-1584, 2004, expressly incorporated herein by reference.

Over the last decade, substantial progress has been made toward buildingcomplete cryocooled digital receiver prototypes that use superconductorADCs. The simplest superconductor ADCs have already demonstratedperformance that compare favorably with the best semiconductor ADCs,which employ complex multi-modulator architectures and massive digitalpost-processing for error correction.

One of the most critical parameters to characterize the performance ofan ADC is its dynamic range. Dynamic range of the ADC is bounded by themaximum signal that can be digitized and the quantization noise ordevice noise floor, whichever is greater. The dynamic range is typicallygiven as a power ratio of the maximum signal to the minimum detectablesignal, in dB, and expressed as a maximum signal to noise ratio (SNR).Equivalently, it may be given as the effective number of bits (ENOB) bythe standard formula ENOB=(SNR[dB]−1.76)/6.02. A related quantity is thespurious-free dynamic range (SFDR), which is given by the ratio betweenthe full-scale power and the largest nonlinear artifact generated by thedata conversion that is present in the output band of the ADC. Forhigh-performance ADCs, it is important to minimize nonlinearities aswell as noise. Digital-to-analog converters (DACs) have similarconsiderations.

Superconductor data converters are based on ideal quantization ofmagnetic flux in units of the flux quantum Φ₀=h/2e=2.07 mV-ps, whereh=Planck's constant and e is the charge on the electron. RSFQ circuitstransport these single-flux-quanta (SFQ) in voltage pulses of height ˜1mV and pulsewidth ˜2 ps, such that the area under each pulse is exactlyΦ₀. In this way, both ADCs and DACs in this technology are practicallyideal and linear. Furthermore, SNR and SFDR of broadband superconductorADCs are among the best in any technology. Still, it is greatlydesirable to increase the SNR and SFDR of a superconductor ADC.

One class of ADCs with an extended dynamic range is a subranging ADC,which combines a coarse ADC, a DAC, and a fine ADC used together in ageneric architecture as shown in FIG. 1. In a subranging ADC with tworanges, the signal to be digitized is split between a coarse ADC and afine ADC. See, U.S. Pat. Nos. 7,365,663, 7,362,125, 7,313,199,7,280,623, 7,038,604, 6,922,066, 6,771,201, 6,750,794, 6,653,962,6,608,581, 6,509,853, 6,331,805, 6,225,936, 6,127,960, 5,936,458,5,731,775, 5,305,006, and 5,272,479, expressly incorporated herein byreference.

In the most ideal case, one may be able to double the number ofeffective bits digitized, sharply increasing the dynamic range. Thebasic approach, as known in the prior art, involves splitting theincoming analog signal into two parts using an appropriate signaldistribution network, one part of which goes to the coarse ADC, whichgenerates a set of digital bits. This digital output is also convertedback to an analog signal in a digital to analog converter (DAC), and iscombined with the second part of the analog input in a subtractor unit,such that most of the signal should cancel out, leaving only a smallresidue signal. Accurate cancellation requires that the DAC besubstantially accurate and linear, and that an appropriate time delayand linear gain amplifier (or attenuator) be included to ensure that thedirect analog signal and the regenerated analog signal are substantiallymatched. The residue signal can then be amplified in a linear amplifierand fed to the fine ADC, which generates another set of digital bits.The most significant bits (MSBs) are combined with the least significantbits (LSBs) in a digital adder (with appropriate digital delay anddigital scaler or multiplier) to generate the combined digital output.

It is important to note that if the DAC is precisely linear and if thegain and delay of the regenerated analog signal are adjusted properly,this subranging ADC can completely compensate for quantization noise andnonlinearity in the coarse ADC. In this case, the performance is limitedonly by the fine ADC. In the ideal case, with a sharply reduced residuesignal, the gain in the amplifier will be large so as to make use of thefull input range of the fine ADC, thus gaining additional bits ofprecision. If one assumes that the full-scale input ranges of the fineADC and the coarse ADC are the same, and if, for example, the residuesignal is a factor of 100 smaller in amplitude than the initial analogsignal, then the gain of amplifier could be as high as 100. This, inturn, could lead to an increase in dynamic range for the subranging ADCof as much as this factor of 100, although this would likely be reducedby various non-idealities. In some cases of the prior art, the fine ADCand the coarse ADC may have different input ranges. For example, thefine ADC may be intrinsically more sensitive (reduced full-scale inputlevel and noise level) than the coarse ADC, in which case the requiredgain of amplifier would be reduced accordingly.

Subranging ADCs have been developed using semiconductor technology ofthe prior art, including a semiconductor DAC and transistor amplifiers.However, it is well known that semiconductor DACs may exhibitsignificant nonlinearity, thus limiting the performance of the overallsubranging ADC. As a way of avoiding this problem, Hansen and Saxeproposed in U.S. Pat. No. 6,489,913, “Subranging ADC using a sigma-deltaconverter,” expressly incorporated herein by reference, an alternativedesign for a subranging ADC as shown in FIG. 2 (taken from this patent).FIG. 2 employs a sigma-delta modulator 12 for the coarse ADC, whichgenerates an oversampled sequence of single-bit output pulses, thelow-frequency spectrum of which corresponds to the input analog signal.This oversampled pulse train is filtered in a digital decimation filter26 to generate a multibit Nyquist-rate digital representation. Thefunction of the DAC is obtained simply by analog filtering thesingle-bit pulse train with a low-pass filter 18 to remove thehigh-frequency quantization noise. Since a passive analog filter istypically quite linear, this DAC is also equally linear, enablingimproved performance in the subranging ADC. In a further aspect of thedesign of FIG. 2, the functions from FIG. 1 of the subtractor and theamplifier are combined in a high-gain differential amplifier 22. To thedegree that the input analog signal and the coarse regenerated analogsignal cancel out, a high linear gain K in this amplifier permitsadditional bits of precision to be generated by the fine ADC 24.

It is of interest to employ high-performance superconductor ADCs in asimilar way to that in Hansen et al., to achieve a subranging ADC withfurther increased dynamic range. Oversampled superconductor modulatorsand digital decimation filters are well known in the prior art. Indeed,Gupta proposed in U.S. Pat. No. 6,489,913, “Subranging Technique UsingSuperconductor Technology”, expressly incorporated herein by reference,how a coarse superconductor ADC and a fine superconductor ADC could becombined to create a subranging superconductor ADC with increaseddynamic range. This is shown in FIG. 3, taken from FIG. 18 of Gupta,where a coarse superconductor ADC based on a Superconducting QuantumInterference Device (SQUID) is combined with a similar finesuperconductor ADC, and a superconductor DAC, to generate additionalbits of precision.

However, superconductor technology does have a serious shortcoming inthe absence of a high-gain linear transistor amplifier. While somesemiconductor amplifiers can operate at cryogenic temperatures, theimpedance and threshold sensitivity are poorly matched to superconductorcircuits, making inclusion of a semiconductor amplifier within asuperconductor circuit generally impractical. Therefore, high-gainlinear amplifiers are difficult to implement in superconductortechnology. Furthermore, although transformers are linear and can beused to achieve current gain or voltage gain, as passive devices theyare unable to achieve power gain. It is difficult to construct asuperconducting subranging ADC without a suitable high-gain amplifier.

SUMMARY OF THE INVENTION

The present invention achieves an improvement by at least providinghigh-gain linear differential amplification in superconductingtechnology, and/or an alternative architecture that substantiallyreduces the required gain factor. Other aspects of the invention willalso be apparent either separately or in combination with the disclosedamplification technologies and/or circuit architecture. Likewise, thevarious embodiments may be used in circuit topologies which may bedifferent than subranging ADCs without departing from the spirit orscope of this disclosure.

One aspect of the present disclosure presents a practical subranging ADCarchitecture using a set of known and novel components that are wellmatched to superconducting device technology. A preferred embodiment ofthe present invention is shown schematically in FIG. 4A.

As described above, superconducting ADCs are based on flux quantizationin units of Φ₀. Magnetic flux is coupled into a superconducting loopwith at least one Josephson junction (essentially equivalent to aSQUID), and the Josephson junction releases the flux in a sequence ofSFQ voltage pulses. If these voltage pulses are counted (digitalintegration), the magnitude of the input flux can be directly measured.This is functionally equivalent to a first-order delta ADC, withimplicit feedback since each pulse automatically reduces the flux in theloop by Φ₀. A delta ADC is an oversampling-type ADC which is known inthe prior art, but is distinct from the better known sigma-delta ADC. Adelta ADC essentially generates the derivative of the incoming analogsignal, and requires the use of a digital integrator following the ADC.Alternatively, a delta ADC may be converted to a sigma-delta ADC by theaddition of an analog integrator in front of the delta ADC. Both deltaand sigma-delta ADCs in superconductor technology are known, but thedelta design may be preferred in some cases.

Such a simple delta ADC is compatible only with a unipolar input signal,since the SFQ pulses are all positive. However, a radio frequency signalis bipolar, and the delta ADC may be modified by the addition of acarrier signal that permits a bipolar input. This is known as a PhaseModulation Demodulation ADC (PMD). Of course, this carrier must besubtracted off in subsequent processing.

For a delta ADC based on the PMD architecture, in the absence of ananalog signal, the single junction SQUID quantizer pulses at the carrierfrequency (f_(car)), which is determined by the average fluxon transportrate through the modulator. When an additional analog input signal iscoupled to the quantizer loop, the timing of each output pulse getsadvanced or retarded in proportion to the derivative of the analoginput. This process encodes the signal derivative into SFQ pulsepositions, which need to be decoded by measuring the pulse positionsagainst a time reference. Hence the phase modulated SFQ pulse stream ispassed to a phase demodulator (synchronizer), which is a clockedsampling circuit that generates a ‘1’ or a ‘0’ indicating whether or notan SFQ pulse arrived during that clock interval. Thus, the synchronizerdecodes the pulse position information into numbers (single-bit in thesimplest implementation, though devices with a higher number of bits maybe implemented). The oversampled digital data and the correspondingclock from the synchronizer then proceed directly to the decimationfilter, where it is first integrated at full speed, and then averagedfurther, reducing the output bandwidth and increasing the effectivenumber of bits.

The use of two PMD ADCs in a subranging architecture is illustrated inFIG. 4C. A received signal is coupled to a coarse ADC and to a fluxsubtractor. The coarse ADC produces an output that represents thereceived signal, with quantization noise resulting from limitedquantization step size. This oversampled bit sequence needs to beintegrated to reconstruct a multibit digital equivalent of the inputsignal. This integrated output may be averaged further and read out atthe decimated rate to reduce the output bandwidth and increase theeffective number of bits. These bits form the most significant bits(MSB) of the subranging ADC. In order to extract the least significantbits (LSB), the oversampled 1-bit coarse ADC output is integrated in ananalog integrator (based on a superconducting inductor), and thenlow-pass filtered to be converted back to the analog domain. Thus, thiscircuit is effectively a DAC with nearly ideal linearity. This analogsignal is then subtracted from the input signal in a “flux subtractor”,a transformer which couples, and effectively subtracts, magnetic fieldscorresponding to properly synchronized and gain-adjusted representationsof the input signal and analog signal from the coarse ADC, to generate aresidue signal representing the error of the coarse ADC. The errorsignal is then digitized by the fine ADC to get the LSBs. The residuesignal, being of lower amplitude than the original signal, is ideally atthe full-scale range of the fine ADC, which may be another PMD ADC whichis similar to the coarse ADC. The digital output of the fine ADC iscombined (e.g., summed) with that of the coarse ADC to yield a digitaloutput with a larger dynamic range (a greater effective number of bits).The output significance of the fine ADC may overlap with the lower bitsof the multibit representation of the coarse ADC, permittingcompensation for various errors.

The design of FIG. 4C avoids the need for an amplifier at the output ofthe flux subtractor. Rather than amplifying the difference, as proposedin the embodiments according to FIGS. 1 and 2, instead this designcouples a small fraction of the input signal to the coarse ADC, andamplifies the output of the coarse ADC by a factor K to restore thesignal component to the same value as the remaining fraction of theinput signal. Given the fact that the combination of the coarse ADC andDAC in superconductor technology conserves magnetic flux, these twoscalings should permit accurate cancellation of the coarse signal in theflux subtractor. If one assumes that the fine ADC and the coarse ADChave the same sensitivity, the factor K corresponds to the additionaldynamic range that the subranging ADC can ideally achieve. For example,if K=64, this corresponds to up to an additional 6 bits of precision.Alternatively, if the fine ADC is intrinsically more sensitive than thecoarse ADC, additional precision may be obtained with a reduced factorof K.

A microwave splitter would be used to direct a small fraction of thepower to the coarse ADC, with the rest going toward the subtractor. Ananalog linear amplifier is difficult to achieve within superconductortechnology, as indicated in the Background section. In a preferredembodiment, this amplifier may be implemented in the digital domain,using active superconducting elements (based on Josephson junctions) toreproduce SFQ pulses either in parallel or sequentially. Circuits toachieve this are described in the detailed specification below. However,by providing an increased energy represented by the digital pulses ascompared to the basic digital stream of “bits”, that is, the quantizedpulses, a power amplification is achievable from the DAC, which alsoacts as a low pass filter.

The inter-range circuitry that integrates the coarse and the fine ADCperforms multiple signal processing functions in the digital and in theanalog domains. One embodiment of this inter-range mixed-signalprocessor incorporates the functions of linear amplification,integration, carrier subtraction, signal subtraction, and filteringtogether in a single integrated device. In another preferred embodimentof the invention, the fine ADC may have a different optimized designthan the coarse ADC. For example, the fine ADC may be substantially moresensitive than the coarse ADC, which would enable increased dynamicrange with a significantly reduced value of K. Alternatively, the fineADC may comprise a sigma-delta ADC, which is less sensitive to highfrequency noise, and hence relaxes the requirements placed on the filterin the inter-range mixed-signal processor (see FIG. 5). Functionalsimulations of several subranging ADC configurations are presented, andshow improvement of up to 35 dB in SNR over a single-stagesuperconducting ADC. A similar improvement of spur-free dynamic range(SFDR) is also expected since the harmonics and inter-modulationdistortion produced by the coarse ADC appear in the residue and aretreated the same way as the quantization error. These distortions willbe substantially cancelled in the final output combining the coarse andthe fine ADC outputs.

A preferred embodiment focuses on the case whereby the coarse ADCgenerates a single oversampled train of SFQ pulses. However, thisapproach is not limited to a single pulse train, but rather can beeasily extended to two or more pulse trains having either equal orunequal weights. Therefore, this approach is compatible with a coarseADC with a multi-bit output.

As may be evident to one ordinarily skilled in the art, otherembodiments based on a variety of ADCs, DACs, filters, integrators,digital amplifiers, and subtractors are also compatible with the basicsubranging architecture described herein.

It is therefore an object to provide an analog-to-digital converter andmethod of conversion, comprising: an input adapted to receive a firstanalog signal; a coarse analog-to-digital converter, adapted to converta first representation of the first analog signal to a first logicalrepresentation of the first analog signal having an associated firstquantized energy per bit; a digital amplifier adapted to produce asecond logical representation based on at least the first logicalrepresentation, having an associated second quantized energy per bit,the second quantized energy per bit being higher by at least 6 dB thanthe first quantized energy per bit, and transform the energy representedby the second logical representation into a second analog signal; asubtractor adapted to combine a time synchronized second representationof the first analog signal and the second analog signal to generate ananalog residue signal representing a difference of the first analogsignal and the second analog signal, the first and secondrepresentations of the first analog signal being respectively scaledbased on at least a relationship between the first quantized energy perbit and the second quantized energy per bit; a fine analog-to-digitalconverter that is adapted to convert the analog residue signal to athird logical representation; and a digital processor, adapted tocombine the first logical representation and the third logicalrepresentation to generate a fourth logical representation whichrepresents the first analog signal with greater precision than the firstlogical representation.

Another object provides a method, and corresponding system, forconverting an analog signal to a corresponding digital representation,comprising: receiving a first analog signal; converting a firstrepresentation of the first analog signal to a first logicalrepresentation of the first analog signal having an associated firstquantized energy per bit; producing a second logical representationbased on at least the first logical representation, having an associatedsecond quantized energy per bit, the second quantized energy per bitbeing higher by at least 6 dB than the first quantized energy per bit;transforming the second logical representation into a second analogsignal; subtracting a time-synchronized representation of the secondanalog signal and a second representation of the first analog signal togenerate an analog residue signal, the second representation of thefirst analog signal being dependent on at least a relationship betweenthe first quantized energy per bit and the second quantized energy perbit; converting the analog residue signal to a third logicalrepresentation; and digitally combining the first logical representationand the third logical representation to generate a fourth logicalrepresentation which represents the first analog signal with greaterprecision than the first logical representation.

At least one of the coarse analog-to-digital converter and the fineanalog-to-digital converter may quantize the input in units of magneticflux. The coarse and/or the fine analog-to-digital converter maycomprise a delta modulator (which may be a phase-modulation-demodulationmodulator), and/or a sigma-delta modulator. The coarse analog-to-digitalconverter is preferably a delta converter employingphase-modulation-demodulation, and the fine analog-to-digital converteris preferably a sigma-delta or delta modulator.

The subtractor may comprise a transformer, and preferably asuperconducting transformer. The transformer may have multiple loops,and may be used to couple energy from a distributed array of drivingelements.

The second logical representation may be transformed into the secondanalog signal with a digital-to-analog converter which comprises atleast one of an integrator and a low-pass filter.

The first logical representation may comprise a series of pulses, andwherein the digital amplifier converts each pulse of the firstrepresentation into a plurality of pulses of the second logicalrepresentation in parallel.

The first logical representation may comprise a series of pulses eachhaving an associated magnetic flux, and wherein the digital amplifierconverts each pulse of the first logical representation to a pulse ofthe second logical representation having an increased total magneticflux with respect to the associated magnetic flux of a pulse of thefirst logical representation.

The digital amplifier may comprise at least one Josephson junction, andmay employ various superconducting technologies.

The digital amplifier is integrated with the subtractor, as well asother possible functions and elements. The integrated digitalamplifier-subtractor may comprise a distributed array comprising aplurality of identical components.

The digital amplifier may receive a fifth logical representation, andperform a logical operation on at least the first logical representationand the fifth logical representation. The fifth logical representationmay thus comprise a phase-modulation carrier, and wherein the logicaloperation comprises a sum or a difference. Thus, the digital amplifiermay, for example, perform a digital subtraction of a carrier wave, orperform other logical data manipulation.

The second logical representation may comprise a single-bit train ofdigital pulses, or at least two parallel trains of digital pulses. Theat least two parallel trains of digital pulses represent signalcomponents of equal logical weight. The at least two parallel trains ofdigital pulses may represent signal components of unequal logicalweight. Generally, each digital pulse on a given line has the samelogical significance as a digital pulse at a different time; however,digital pulses at various times may also have different significance,which may be encoded based on a digital pulse power (duration, height,etc.) or an interpretation of the pulse by a receiving device.

At least one of the fine and coarse analog-to-digital converters maycomprise a digital filter. The digital filter may comprise a digitalintegrator. The digital filter may comprise a decimator that reduces theoutput sampling rate.

The system may also comprise a digitally adjustable time delay, adaptedto synchronize the first and second representations of the first analogsignal.

The coarse analog-to-digital converter may have at least twoquantization thresholds.

A further object provides a method of subranging analog-to-digitalconversion, and corresponding apparatus, wherein:

(a) a first representation of a first analog signal is converted to afirst oversampled train of digital pulses in a coarse analog-to-digitalconverter having a first digital pulse energy;

(b) the power in the first oversampled train of digital pulses isamplified to generate a second oversampled train of digital pulsescharacterized by at least one of having a second digital pulse energygreater than the first digital pulse energy and having a larger numberof pulses of the first digital pulse energy than the first oversampledtrain of digital pulses;

(c) the second digital pulse train is converted back to a second analogsignal;

(d) the represented power and timing of a second representation of thefirst analog signal and the second analog signal being adjusted toachieve a good match at a subtractor;

(e) the timing and power adjusted representation of first and secondanalog signals are subtracted in the subtractor to generate a residuesignal;

(f) the residue signal is converted to a corresponding digitalrepresentation; and

(g) the corresponding digital representation is combined in a digitalprocessor with the information in the first oversampled train of digitalpulses to generate a digital signal that represents the first analogsignal with greater precision than the information in the firstoversampled train of digital pulses.

The conversion of at least one of the conversion of the first analogsignal to a first oversampled train of digital pulse and the conversionof the residue signal to a corresponding digital may be based upon thenatural quantization of magnetic flux in superconducting loops.

The corresponding apparatus may comprise an integrated inter-range dataprocessor which amplifies a power of the first train of digital pulses,converts the second train of digital pulses to the second analog signal,and subtracts the first and second analog signals. The inter-range dataprocessor may perform at least one function selected from the groupconsisting of integration, filtering, time-shifting, and carriersuppression.

A still further object provides an inter-range mixed signal processorcomprising a digital amplifier adapted to produce a second logicalrepresentation having an associated second quantized energy per bitbased on a first logical representation having an associated firstquantized energy per bit, the second quantized energy per bit beinghigher by at least 6 dB than the first quantized energy per bit andtransform the energy represented by the second logical representationinto a first analog signal, a subtractor adapted to combine the firstanalog signal and a second analog signal to generate an analogdifference signal.

The inter-range mixed signal processor may further comprise a logicalarray adapted to perform a logical function on a third logicalrepresentation and the first logical representation to produce thesecond logical representation.

The inter-range mixed signal processor may further comprise at least oneof an analog filter and a digital filter, an integrator, and/or a timedelay. These elements may be static, adjustable or controlled, oradaptively controlled, for example. Thus, for example, a time delay maybe adaptively controlled to synchronize signals to achieve a maximumcorrelation there-between.

These and other objects will become apparent from a review of theapplication as a whole, and the recited objects are not to be deemedlimiting on the scope of the invention. The various functions and/orelements disclosed herein may be used separately, in the variousfeasible subcombinations and permutations, and/or together, withoutdeparting from the spirit and scope of the invention.

BRIEF DESCRIPTION OF THE DRAWINGS

The foregoing summary, as well as the following detailed description ofthe embodiments of the present invention, will be better understood whenread in conjunction with the appended drawings. For the purpose ofillustrating the invention, there are shown in the drawings embodimentswhich include those presently preferred. As should be understood,however, the invention is not limited to the precise arrangements andinstrumentalities shown.

FIG. 1 shows a prior art block diagram of a generic subranging ADC.

FIG. 2 shows a prior art block diagram of a subranging ADC that uses anoversampling sigma-delta modulator for the coarse ADC.

FIG. 3 shows a prior art conceptual block diagram of a subranging ADCthat uses a SQUID-based ADC for both the fine ADC and the coarse ADC.

FIG. 4A shows a block diagram of an embodiment of a subranging ADC,comprising two oversampled delta modulators for the two ranges and aninter-range mixed-signal processor.

FIG. 4B shows a block diagram of an embodiment of a superconductorsubranging ADC, comprising two oversampled delta modulators for the tworanges, each producing an output in the form of a stream of single fluxquanta, and a corresponding inter-range mixed-signal processor,comprising a fluxon amplifier and a flux subtractor.

FIG. 4C shows a block diagram of an embodiment of a superconductorsubranging ADC, comprising two oversampled phase modulation-demodulation(PMD) delta modulators for the two ranges, each producing an output inthe form of a stream of single flux quanta, and a correspondinginter-range mixed-signal processor, comprising a differential fluxonamplifier to subtract the phase modulation carrier from the coarse ADC.

FIG. 4D shows a block diagram of an embodiment of a superconductorsubranging ADC, comprising two oversampled phase modulation-demodulation(PMD) delta modulators for the two ranges, each producing an output inthe form of a stream of single flux quanta, and a correspondinginter-range mixed-signal processor, comprising a digital carriersubtractor and a differential fluxon amplifier.

FIG. 5 shows a block diagram of a preferred embodiment of a subrangingADC, comprising an oversampled delta modulator for the first (coarse)ADC range, an oversampled sigma-delta modulator for the second (fine)ADC range and an inter-range mixed-signal processor.

FIG. 6 shows a Simulink model for low-pass subranging ADC using phasemodulation-demodulation delta modulators for both coarse and fineranges.

FIG. 7A shows a simulated power spectrum for the phasemodulation-demodulation delta ADC and phase modulation-demodulationsubranging delta ADC. The spectrum is for 9.7 MHz sine wave beingsampled at 20.48 GHz. The output bandwidth is 40 MHz.

FIG. 7B shows the SNR of subranging ADC as a function of amplificationfactor (K) of the coarse ADC output for a 9.7 MHz sine wave beingsampled at 20.48 GHz.

FIG. 8 shows the SNR vs. signal power for the phasemodulation-demodulation delta ADC and phase modulation-demodulationsubranging delta ADC. The spectrum is for 9.7 MHz sine wave beingsampled at 20.48 GHz.

FIG. 9A shows the simulated spectra for 28 MHz signals with 40-GHzsampling frequency and an amplification factor (K) of 128.

FIG. 9B shows the simulated spectra for 156 MHz signals with 40-GHzsampling frequency and an amplification factor (K) of 128.

FIG. 10 shows the SNR performance in 313 MHz bandwidth for a coarse ADCcomprising a PMD delta modulator and a fine ADC comprising another PMDdelta modulator with clock 40 GHz and the amplification factor of 128.

FIG. 11 shows a Simulink model for a low-pass subranging architectureusing delta modulator for the coarse ADC and sigma-delta modulator forthe fine ADC.

FIGS. 12A, 12B and 12C show, respectively, the simulated spectrum forinput signals of 28.125 MHz, 276.875 MHz, and 476.875 MHz, sampled witha 40.96 GHz clock and an amplification factor of 128.

FIG. 13 shows the SNR performance in 10 MHz BW for the low-passsubranging ADC with a coarse ADC comprising a PMD delta modulator and afine ADC comprising a sigma-delta modulator with clock 40.96 GHz and anamplification factor of 128.

FIG. 14A shows the flux subtractor comprising multiple transformersconnected in a common loop, in which the inversion of the coarse ADCoutput is achieved by reversing the winding of the coupling coil; for aPMD ADC, the phase modulation carrier or the flux pump is subtracted togenerate a bipolar waveform.

FIG. 14B shows the flux subtractor corresponding to the digital carriersubtraction scheme depicted in FIG. 4D.

FIG. 15 shows a flux subtractor with a distributed secondary (residue)inductor accommodating multiple fluxon injectors attached to the digitalfluxon amplifier.

FIG. 16A shows a mixed-signal circuit scheme involving a digitalmulti-tap fluxon amplifier feeding a set of small fluxon injector tapsperforming both analog subtraction and integration functions, in whichthe pick-up coil is considered as a series of smaller coils each coupledto an injector tap coil.

FIG. 16B shows the schematic of a Josephson junction (JJ) circuit forthe fluxon amplifier tap of FIG. 16A with representative values of JJcritical current (in mA), inductor values (in pH) and bias currents (inmA).

FIG. 17 shows a fluxon amplifier block attached to an n_(tp)-tap coilcoupled to the pick-up coil and the residue coil.

FIG. 18A shows a mixed-signal circuit scheme involving a digitalmulti-tap fluxon amplifier, with built-in lowpass filtering function,feeding a set of small fluxon injector taps performing both analogsubtraction and integration functions. Each fluxon amplifier tapcontains digital (clocked) and analog (JTL ladder) delay elements toperform low-pass filtering for both inputs.

FIG. 18B shows the effect of digital and analog filtering withconceptual flux vs. time diagrams.

FIG. 19 shows a fluxon amplifier block built-in lowpass filteringfunction attached to an n_(tp)-tap coil coupled to the pick-up coil andthe residue coil.

FIG. 20 shows a multi-function mixed-signal block comprising a fluxonamplifier block, a multi-tap fluxon injector coil (M1) coupled to aresidue coil (R1) and a pick-up coil (P1), in which unwanted fluxcoupling (Φ₁₃) between R1 and P1 is cancelled out by another pair ofresidue coil (R2) and pick-up coil (P2), coupled with opposite sense,and the inductance of the pick-up coil (P1+P2) forms a segment of atransmission line with the capacitor (C′).

FIG. 21 shows a scheme for doubling the amplification factor withoutincreasing the residue inductance by combining four multi-functionmixed-signal blocks.

FIG. 22 shows a subranging scheme with a coarse ADC comprising amulti-threshold modulator producing a q-bit code, where each bit is ofequal significance; a corresponding inter-range mixed-signal interfacecomprising q N-tap fluxon amplifier blocks and a subtractor; an n-bitfine ADC; and a digital processor for appropriately combining it withthe m-bit coarse ADC output.

FIG. 23 shows a subranging scheme with a coarse ADC comprising amulti-threshold modulator producing an m-bit binary code, acorresponding inter-range mixed-signal interface comprising a set offluxon amplifier blocks with binary amplification factors and asubtractor, an n-bit fine ADC, and a digital processor for appropriatelycombining it with the m-bit coarse ADC output.

FIG. 24 shows a subranging scheme with a coarse ADC comprising amulti-threshold modulator producing an m-bit binary code, acorresponding inter-range mixed-signal interface comprising a digitalm-bit-in, k-bit-out look-up-table for gain adjustment, a set of fluxonamplifier blocks with binary amplification factors, and a subtractor, ann-bit fine ADC, and a digital processor for appropriately combining itwith the m-bit coarse ADC output.

FIG. 25 shows the block level schematic used to simulate the delta-deltasubranging ADC with a 4-tap inter-range mixed signal processor, in whichtwo similar flux quantizers are used in the PMD coarse and finemodulators.

FIG. 26 shows the simulation result of the delta-delta subranging ADC ofFIG. 25 with a 4-tap inter-range mixed signal processor.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

The subranging approach is widely used for high-performance ADCs toincrease dynamic range. In a subranging ADC, the signal to be digitizedis split, going to a coarse ADC and a fine ADC. The output from thecoarse ADC is subtracted from the input, forming a residue signal thatis essentially the coarse ADC's quantization error. Upon digitization ofthis residue signal with finer resolution in a fine ADC, we can sum thetwo ADC outputs and get cancellation of the coarse quantization error.Therefore, we simultaneously obtain the high maximum signal level of thecoarse ADC and the fine quantization steps of the fine ADC, resulting ina much higher dynamic range than either ADC. In other words, the outputsfrom the coarse and fine ADC's form the most significant bits (MSB) andleast significant bits (LSB) respectively of the subrangingarchitecture.

With only one type of modulator, such as a low-pass delta modulatorbased on the principle of phase modulation-demodulation (PMD), we canobtain enhanced dynamic range by residue amplification. A typicalmodulator generates an oversampled 1-bit differential code thatrepresents the discrete derivative of the input signal. This 1-bitoversampled code needs to be integrated first to reconstruct the digitalequivalent of the input signal, and then averaged further and read outat the decimated rate to reduce the output bandwidth and increase theeffective number of bits. These m bits form the most significant bits(MSB) of the subranging ADC. In order to extract the least significantbits (LSB), the oversampled single bit stream from the coarse ADC outputis converted back to the analog domain in a DAC and subtracted from theinput signal to generate a residue signal representing the error of thecoarse ADC. The error signal is then digitized by the fine ADC to getthe LSBs. Ideally, the residue signal has a dynamic range equivalent tothe dynamic range of the fine ADC. In a known implementation of asubranging ADC, the residue signal is extremely small, and needs to beamplified to the full-scale range of the fine ADC. The n-bit digitaloutput of the fine ADC is divided by the amplification factor and summedwith the coarse ADC output to yield a digital output with a largerdynamic range (more effective bits).

Instead of amplifying the analog residue, one can move the amplificationbefore the subtraction function in the digital domain. To do this, wedivide the signal between the two ADCs (FIG. 4), coupling a smallfraction to the coarse ADC and the rest to the fine ADC. Thus, thedivision is typically unequal, thus supporting a large dynamic range foreach of the coarse and fine ADCs. Now, the coarse ADC output needs to beamplified by the same factor (K) to match the amplitude of the analogsignal being applied to the subtractor. In a preferred embodiment, theinterface between the two ADCs, called the inter-range mixed-signalprocessor, performs several signal processing functions: subtraction,filtering, amplification, and in the case of using a delta modulator inthe coarse ADC, integration. The amplification and filtering functionscan be done in both analog and digital domains. Digital amplification,or multiplication, ensures linearity, and is particularly preferred.Additional digital processing to compensate for nonidealities ofsubsequent analog components, such as the subtractor, may also beperformed in the digital domain. The analog filter performsdigital-to-analog conversion of the single-bit oversampled data stream;no explicit device is needed. Following digital integration andfiltering, the coarse ADC output is multiplied by K and summed with thesimilarly processed fine ADC output.

Superconductor low-pass delta modulators have demonstrated highlinearity in data conversion. FIG. 4B shows a subranging ADC comprisingtwo delta modulators (See Reference 4). The output of such a deltamodulator is a stream of single flux quantum pulses. The correspondinginter-range mixed-signal processor includes a fluxon amplifier and aflux subtractor. Any other digital processing, such as filtering, of thecoarse ADC's delta modulator will have to be performed with appropriatedigital logic, such as rapid single flux quantum logic (RSFQ). Ourcurrent preferred implementation of a superconductor delta modulatoruses the phase modulation-demodulation (PMD) architecture (Reference 4).The PMD delta modulator uses a stream of flux quanta at half the maximumfluxon transport rate of one Φ₀ every clock period as the phasemodulation carrier. In the simplest case, this carrier is generated bypumping flux in the phase modulator circuit at half the sampling clockrate (f_(clk)/2). The flux pump allows unipolar digital coding: when theinput signal is absent the output is a pattern of alternating 1's and0's, when the input signal is present the output has more 1's (0's) whenthe signal derivative is positive (negative). Therefore, this carriermust be subtracted before subtraction from the analog input signal.

One method of doing this is to construct a differential fluxon amplifierthat receives the coarse ADC's PMD delta modulator output and a copy ofthe carrier (or flux pump) at its two differential inputs (FIG. 4C).Another method of subtracting the carrier is to do it digitally andgenerate two differential unipolar streams (FIG. 4D).

The subtraction function is performed by subtracting magnetic fluxproduced by the analog input and the amplified digital output from thecoarse ADC's PMD delta modulator using a set of coupled coils. Forexample, we can construct three sets of coils, the first carrying theanalog input signal, the second carrying the output of the digitalfluxon amplifier, and the third carrying the residue into a fine ADC;the coupling of the first (pick-up coil) and the second (fluxon injectorcoil, which may comprise multiple taps) to the third (residue coil) musthave opposite sense for subtraction. The digital amplifier produces abipolar signal of magnitude KΦ₀/2 of either polarity and injects thecorresponding flux into a residue coil.

The effect of unfiltered quantization noise is particularly severe on adelta ADC, since the slew-rate contribution is proportional to thefrequency of the noise component extending all the way up to f_(clk)/2,which may be 2-3 orders of magnitude higher than the RFsignals-of-interest. If we set a performance criterion of 90-dB SNR in10-MHz bandwidth, a 2^(nd)-order low-pass filter is adequate for inputfrequencies less than 200 MHz. Over 200-MHz, the filtering requirementfor a delta+delta subranging ADC will be severe (requiring a 7^(th)order bandpass filter for f=500 MHz, according to initial simulations).One way of avoiding this required level of filtering is to use adelta-sigma modulator, which is not slew-rate limited, as the fine ADC(FIG. 5).

A functional MATLAB Simulink model, as shown in FIG. 6, was developedfor the subranging architecture and used to carry out simulations toanticipate the improvement in performance of a two-range subranging ADCover a single-range ADC, using two identical low-pass PMD deltamodulators.

As seen from FIG. 6, the output from the coarse ADC is passed through alow-pass Bessel filter and integrated in an analog integrator. To matchdelay and amplitude attenuation, the analog input signal is alsofiltered before being applied to the fine ADC. The phase modulationcarrier is subtracted also. The resultant signal is amplified and thensubtracted from the analog input before being digitized by the second(fine) ADC. The oversampled data from the coarse and fine ADC areintegrated and averaged further in a digital decimation filter. Thecoarse ADC output needs to be delayed to compensate for the delaythrough the inter-range mixed-signal processor before being summed withthe fine ADC output.

FIG. 7A shows the simulated power spectrum for the phasemodulation-demodulation delta ADC and phase modulation-demodulationsubranging delta ADC. The spectrum is for a 9.6875 MHz sine wave beingsampled at 20.48 GHz and decimated by a factor of 256. The cutofffrequency of the analog low-pass filter is 80 MHz. The amplificationfactor (K) is 128. As seen from FIG. 7A, the noise floor of thesubranging ADC is significantly lower than that of the regular low-passPMD ADC. At the signal peak, the two traces overlap, confirming correctoperation. Both the coarse and fine ADCs use a single channelsynchronizer (Reference 4). FIG. 7B plots the calculated signal-to-noiseratio (SNR) as a function of the amplification factor (K). For loweramplification values (up to 8), the performance of the subranging ADC issimilar to that of the single modulator ADC. One plausible explanationis that the amplitude attenuation in the lowpass filter nullifies anyperformance enhancement. For simulation, a simple Bessel filter from theSimulink tool box was employed. Improved design of the analog filter,reducing the passband attenuation, would enable enhanced SNR even forlower amplification ratios.

FIG. 8 plots the SNR for a PMD delta ADC and a two-range PMD deltasubranging ADC as a function of the signal power (in dB full scale). Tojustify the accuracy of simulation, measured results for the PMD ADC arealso plotted. The measured results are in close agreement with thesimulated performance. The subranging ADC shows a 32 dB gain in SNR atsignal power close to the slew rate limit. The simulation does not takeinto account implementation losses like the imperfections in phase delaymatching which might drop the projected gain in performance; however, adigitally controlled phase delay network may be employed as necessary(not shown in the figures), and therefore this is not an insurmountablepractical limitation in implementation. Such a delay network may beadaptive, especially if there is an overlay in the range of the coarseand fine ADC, since this permits a correlator to find and maintain anideal phase delay to maximize the correlation of the lower coarse ADCbits and upper fine ADC bits in the overlapping range. Typically, acontrollable phase delay network would not be required, and a fixeddelay in a static design would suffice.

FIGS. 9A and 9B show the simulated power spectra for a 28 MHz and a 156MHz sinusoidal input respectively, both clocked at 40 GHz with anamplification factor (K) of 128. The two-range PMD delta subranging ADCis slew-rate limited. Therefore, its SNR drops as the input analogsignal frequency is increased. FIG. 10 shows a plot of the SNR in thefull output bandwidth of 312.5 MHz (f_(clk)/2R, where the sampling clockfrequency f_(clk) is 40 GHz and the decimation ratio R is 64), as afunction of input analog signal frequency.

Another subranging ADC implementation, substituting the delta modulatorwith a sigma-delta modulator in the fine ADC, improves the performanceat higher analog signal frequency. FIG. 11 shows the correspondingMATLAB Simulink model. A second-order low-pass Bessel filter is used toreject out-of-band quantization noise. In order to avoid phase mismatchbetween coarse ADC output and analog input signal due to the low-passfilter, the filter is moved after the subtractor. A compensating delayis inserted in the coarse ADC output path to avoid misaligned phaseswhile summing the coarse and fine ADC outputs. A current-to-voltageconverter converts the residue current to voltage which is furtherdigitized by the sigma-delta modulator. The coarse and fine ADC outputsare added in software and their spectra are analyzed.

Extensive simulations of the subranging ADC architectures were carriedout using a delta PMD ADC modulator for the coarse and a delta-sigmamodulator for the fine sections of the subranging ADC. Simulation forinput frequencies 8, 28, 88, 116, 156, 223, 273, 323, 377, 423, 477, 523MHz was performed. Simulations were done for clock frequencies of 40.96GHz and amplification coefficients of 128. Representative spectra (FIGS.12A, 12B, and 12C) and a summary of SNR as a function of signalfrequency with 10 MHz instantaneous bandwidth (FIG. 13) are shown.

The inter-range mixed-signal processor performs several functions:subtraction, amplification, integration, filtering, and delay.

The basic concept of a flux subtractor is shown in FIG. 14A. The analoginput and the coarse ADC outputs are inductively coupled to two seriallyconnected coils with opposite polarity. The difference or the residuesignal, Φ_(residue)=Φ_(in)−Φ_(coarse), is fed to the fine ADC. The rawsingle-bit oversampled coarse delta ADC output needs to be integratedfirst to reconstruct the input signal. Furthermore, in a PMD ADC, acarrier signal (called flux pump) is added to the input at the rate ofΦ₀f_(clk)/2. This may be thought of as an offset ‘ramp’ which uponintegration yields a dc offset equal to half of full-scale. Beforesubtraction from the analog input, the flux pump needs to be subtractedalso. This is done by injecting the coarse ADC output and the flux pumpfrom the opposite ends of a large inductor (L_(int)) that also performsthe integration function. A lowpass filter, which is not shown in theschematic, is provided to reject the out-of-band quantization noise.FIG. 14B shows the scheme corresponding to digital carrier subtractionshown in FIG. 4D. However, the extremely higher inductance (L_(int))required to integrate the full-scale signal results in very low energycoupling to the residue coil (L_(res)).

A preferred approach is to couple a small fraction of the input signalto the coarse ADC and then amplify its output before subtraction withthe rest of the analog input. The best way to ensure linearity inamplification is to perform it in the digital domain by producing Kcopies of the SFQ pulse stream and injecting them into the residue coil.A structure for this amplification is a network of active Josephsontransmission line (JTL) splitters. Instead of a single coil carrying thecoarse ADC output (and the flux pump), a series of fluxon injector coilsare provided, each being driven by a splitter segment, coupling tomultiple residue coils in series. This is shown in FIG. 15. This schemereduces the inductance of each tap to L_(dint)=L_(int)/K, therebyimproving the energy coupling K-fold. Even for a large amplificationfactor (K=128), the resulting L_(dint) may still be too large for thedesired high energy coupling. The higher L_(dint) also increases theresidue inductance (L_(res)), and therefore, the noise floor.

A preferred solution is to restrict the residue inductance to obtain alow enough noise floor. To understand the solution, it is instructive toreverse the challenge. First, we fix the total residue inductance to getthe desired noise floor, which makes each segment (L′_(res)=L_(res)/K).In order to achieve higher energy coupling, the corresponding fluxoninjector tap (L_(tp)) needs to be significantly reduced. This, in turn,limits the maximum signal that can be integrated to N·Φ₀/L_(tp)<I_(c),where I_(c) is the critical current of the junctions in the injectortap. This restricts N to 2-3, which is much, much less than the desiredfull-scale signal (˜40,000Φ₀/K for f_(clk)=40 GHz). Even for a largeamplification factor (K=128), we have a difference of two orders ofmagnitude in the number of flux quanta that each fluxon injector coilcan store.

Since we are only interested in the small difference between two largequantities, one approach is to combine the subtraction function with theamplification. A preferred solution provides distributed fluxsubtraction and amplification. In this scheme, the coarse ADC output isintegrated in multiple injector taps, each with a very small inductance.Full-scale signal integration is enabled by restricting the integratedcurrent in each tap to be below critical current (I_(c)). This isaccomplished by enabling distributed subtraction by coupling the pick-upcoil, carrying the input analog signal, strongly to each of the K tapsof the multi-tap coil carrying the amplified coarse ADC output. Theinput signal continuously subtracts from the signal being integrated inthe injector taps, thereby preventing it from exceeding the thresholdI_(c).

This distributed subtraction scheme, shown in FIG. 16A is different froman alternative scheme where the integration of the coarse ADC output wasdone first, and the resultant analog signal then amplified beforeperforming subtraction (Reference 1). In the present scheme shown inFIG. 16A, first the coarse ADC output (and the carrier) is amplified bydigital multiplication. Each segment (tap) of this fluxon amplifiercomprises a splitter that produces an SFQ pulse propagating to the nextsegment and another that is injected into the L_(tp) inductor. Next, theintegration and the subtraction functions are merged together in a setof injector tap coils. The residue current, which represents the errorof the coarse ADC is now integrated in these injector coils and is readout by coupling them with a common residue coil, as shown in FIG. 17.The residue is then digitized by the fine ADC. The fluxon amplifier isdivided into several blocks, each feeding a set of n_(tp) injector tapcoils. Each fluxon amplifier block has a gain of n_(tp) and has twodifferential inputs (D and C), representing the coarse ADC's deltamodulator output and its carrier respectively. The multi-tap injector iscoupled (Φ₁₂) to a pick-up coil (P1). It is also coupled (Φ₂₃) to aresidue (R1). There is also direct coupling of flux (Φ₁₃) between thepick-up and the residue coils.

FIG. 16B shows the circuit schematic of a fluxon amplifier tap. Eachdigital input stream, representing the coarse ADC's delta modulatoroutput or its carrier, is split into two copies, the first going to thefluxon injector coil and the second propagating on to the correspondinginput of the next segment.

Another function that may be incorporated in this mixed-signalprocessing circuit block is low-pass filtering. The filtering is done byproducing time-delayed copies of a signal and combining them. FIG. 18Ashows a scheme for introducing the filtering function within each fluxonamplifier tap. First, a digital delay stage is introduced to delay byone or more clock periods. This acts as a digital filter, as representedin FIG. 18B, reducing the step-size of the staircase function of theinjected flux as a function of time. Second, finer analog filtering canbe done by introducing a ladder of JTL splitters and adding the splitfluxon in parallel inductors. The delay through the JTL may be varied bychanging its bias current to obtain the best filtering. FIG. 19 shows afluxon amplifier block with built-in filtering and a gain equal to thenumber of taps (n_(tp)).

FIG. 20 shows a multi-function mixed-signal block comprising a fluxonamplifier block attached to a multi-tap fluxon injector coil (M1). Themulti-tap injector is coupled (Φ₁₂) to a pick-up coil (P1). It is alsocoupled (Φ₂₃) to a residue (R1). However, direct coupling (Φ₁₃) betweenthe pick-up and the residue coils is inevitable and undesired.Fortunately, this can be negated by using another set of coils ofreversed sense in series. A transmission line structure for the inputanalog signal to travel between multi-function mixed-signal blocks maybe created by using an appropriately valued capacitor (C′).

In order to increase the amplification factor, several of thesemulti-function mixed-signal blocks are connected in series. However, theseries connection proportionally increases the residue inductance andhence the noise floor of the fine ADC. In order to maintain the residueinductance constant, an equal number of blocks need to be connected inparallel. Thus, every doubling of the power amplification necessitatesquadrupling the hardware. FIG. 21 depicts a scheme of connecting 4multi-function mixed-signal blocks to double the gain. The data (D) andthe carrier (C) propagation have to match that of the analog inputsignal. This is accomplished by using a driver-receiver pair tointerface SFQ pulses on a passive transmission line (PTL) (Reference 3).

Multi-threshold delta and sigma-delta modulators produce higherintrinsic dynamic range. FIG. 22 shows a subranging scheme for usingsuch a multi-threshold modulator in the coarse ADC. For example, the PMDADC with multi-channel synchronizer produces thermometer-coded multi-bitoutput, which is subsequently added to produce an m-bit binary weightedsignal for interfacing with a digital processor, such as acascaded-integrator-comb (CIC) digital decimation filter (Reference 2).The inter-range mixed-signal processor for such a multi-threshold coarseADC modulator may be constructed with the same basic building blocksdescribed for the subranging ADC with single threshold modulator (FIG.4A). In the scheme shown in FIG. 22, there are q bitstreams of equalsignificance which are amplified by a factor of N each with the digitalfluxon amplifier blocks, with or without built-in low-pass filtering.These blocks are combined with a subtractor comprising a multi-tap fluxinjector coil also performing the function of integration.Digital-to-analog conversion takes place in the boundary between thefluxon amplifiers and the fluxon injector coils. It is also possible totake the binary-weighted m-bit output after the adder in the coarse ADC(FIG. 23). In this case, the bits must be amplified according to theirsignificance. If the least significant bit is amplified N times, themost significant bit must be amplified by a factor of 2^(m-1)N. Thebinary-weighted numbers offer more compact digital logic implementationswhich are advantageous for extending the inter-range digital processing.For example, further adjustments of gain may be necessary to compensatefor gain mismatches between the coarse and fine ADC analog inputs andfor non-ideal transformer coupling. A programmable digital look-up tableplaced within the inter-range processor, as shown in FIG. 24, provides amethod to adjust gain.

FIG. 25 shows the block level schematic used to simulate the delta-deltasubranging ADC. Two similar flux quantizers are used in the PMD coarseand fine modulators. A fraction (1/K) of the full-scale input signal((1+K)/K) is applied to the coarse ADC, while the rest is applied to thefine ADC. The intrinsic slew rate limit of this flux-quantizing ADC is asingle flux quantum (Φ₀) in each sampling interval. Therefore, the mostnatural configuration for the flux pump is to inject fluxons at Φ₀/2 persampling period, to accommodate bipolar input signals ±Φ₀/2 per samplingperiod. This is done by pumping fluxons at a frequency off_(pump)=f_(clk)/2. Thus, in the absence of the input signal, both thequantizers pulse at the pump frequency. When an additional input signalis coupled to the quantizer loop, the pulse positions either advance orretard in proportion to the derivative of the input signal, thusproducing a phase modulated pulse stream at the quantizer output. Thisphase modulated pulse stream is demodulated by the synchronizer, whichis a clocked sampling circuit generating a ‘1’ or ‘0’ indicating whetheror not a pulse arrived in a given clock period. This 1-bit oversampleddifferential code from the synchronizer is then digitally integrated,filtered, and amplified by K to generate the m most significant bits ofthe subranging ADC. This digital processing of the coarse modulatoroutput to generate m bits appropriate significance is not shown in theschematic.

To generate the additional n bits, the coarse modulator output isfurther processed by the inter-range mixed signal processor. The digitaldata from the coarse ADC is amplified by digitally multiplying the SFQpulses and integrating each pulse in different taps (L_(tp)) of themulti-tap coil. A 4-tap inter-range processor is used for simulation.The unipolar to bipolar conversion of the coarse modulator is achievedby digitally subtracting the carrier by injecting it from the oppositeend of each tap. The coarse modulator output needs to be lowpassfiltered to reject the out of band quantization noise. The filteringfunctionality is merged in the amplification process by digitallydelaying the inputs to the multiple taps, thus reducing the step size ofthe integrated signal to generate a more smoothly changing signal (FIGS.18A, 18B). Similarly, to filter the carrier, two 180 degrees phaseshifted carriers (PH1 and PH2) are generated from the master clock; PH1being used to subtract carrier from odd numbered taps and PH2 being usedto subtract carrier from the even numbered taps.

To integrate the full-scale signal, L_(tp) needs to be large enough tointegrate a few hundred fluxons (˜300 for 10 MHz input signal, sampledat 40 GHz). However, to reduce the noise floor the residue inductanceshould be very small, and to increase the energy coupling between eachtap and the residue coil, the tap inductance needs be extremely small.Hence, the saturation current of L_(tp) is chosen so as to integrate amaximum of two fluxons per tap. On exceeding the saturation current, thefluxon is not integrated but released by unintended switching of thecarrier port junction. To enable full-scale signal integration whileusing a very small tap inductance, the integration and subtractionfunctions are merged, so as to restrict the residual current per tap tobe lower than the saturation limit of L_(tp). This is accomplished byenabling distributed subtraction by coupling the input coil strongly toeach of the taps of the multi-tap coil. The input signal continuouslysubtracts the signal being integrated in each tap, thereby preventing itfrom reaching the saturation limit of the tap inductor. An inevitableand undesired consequence of this scheme is a direct coupling (Φ₁₃)between the input and the residue coils. Fortunately, this can benegated by using another coil or reversed polarity in series (−4 Φ₁₃ inFIG. 25). The residual current in each tap represents the error of thecoarse ADC and is integrated by coupling each tap with a common residuecoil. The integrated residue is then digitized by the fine modulator(only the fine quantizer is shown in the schematic). In FIG. 25, allblocks not otherwise labeled are active Josephson transmission linesegments for either digital signal propagation or splitting.

FIG. 26 shows the circuit-level simulation result of the delta-deltasubranging ADC with a 4-tap inter-range mixed signal processor. The sameanalog input is applied to the coarse and fine ADC. However, thecoupling coefficient of the coarse ADC input transformer is K timessmaller, resulting in a factor of K smaller input signal being coupledto the coarse ADC. The carrier represents a copy of SFQ pulses beingapplied to the pump which is then smoothed out by the pump to generate aslowly changing current. The carrier signal is applied at half the clockfrequency. In the absence of input signal, the coarse ADC output(synchronizer) generates a ‘1010’ pattern which is then modulated by theinput signal. For example, the three consecutive ‘1's’ in the coarse ADCoutput pattern is a consequence of modulation of the carrier by theinput signal. The clock phases represent the two phase shifted carriersbeing used for unipolar to bipolar conversion of the coarse ADC output.I(Res) represents the current in the residue inductor, which is the sumof the current due to the carrier and the integrated residual currentfrom the multiple tap inductors. For low clock frequency simulations,two distinct changes in residual current can be identified; onecorresponds to injection of carrier, and the other corresponds to signalsubtraction in the tap inductors. The fine quantizer output shows thepropagation of the carrier, representing significant cancellation of theanalog input to the fine ADC such that the residual error beinggenerated is smaller than the flux resolution of the fine quantizer.Other simulations have verified the phase modulation of the fine carrierby the residual current. The penultimate trace shows the data andcarrier pulses being injected in tap1. The pulses encircled with dashedlines represent the excess pulses in coarse ADC output because of theinput signal; whereas the other pulses correspond to the carrier of thecoarse ADC. The fluxons being applied to the carrier port of theinter-range interface overlap with the carrier pulses in the coarse ADCoutput, and are indistinguishable in the figure. Finally, the last tracerepresents the current being integrated in the first tap. Here again,two distinguishable processes can be identified: one corresponds to theincrease in current corresponding to fluxon injection from coarse ADC inresponse to input signal and the subsequent subtraction because of thecoupling to the fine analog input signal, and the second processcorresponds to carrier subtraction of the coarse ADC in the inter-rangeinterface that results in spikes in the tap current.

It should be appreciated that changes could be made to the embodimentsdescribed above without departing from the inventive concepts thereof.It should be understood, therefore, that this invention is not limitedto the particular embodiments disclosed, but it is intended to covermodifications within the spirit and scope of the present invention asdefined by the appended claims.

REFERENCES (EACH OF WHICH IS EXPRESSLY INCORPORATED HEREIN BY REFERENCE)

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What is claimed is:
 1. A subranging superconducting analog to digitalconverter, comprising: a splitter, configured to receive a first analogsignal and provide a first portion and a second portion having anapportionment ratio; a coarse analog to digital converter portionreceiving the first portion, and comprising a first delta modulatorconfigured to generate a first single bit stream of oversampled digitaldata, which is fed to a first digital integrator and a first digitalfilter to produce a coarse analog to digital converter output; aninter-range mixed signal processor receiving the second portion,configured to receive the first single bit stream of oversampled digitaldata from the first delta modulator, comprising a circuit configured togenerate a second analog signal corresponding to the single bit streamof oversampled digital data from the delta modulator, an analogsubtractor, and at least one delay, configured to time-align thegenerated second analog signal with the second portion to generate adifference signal; a fine analog to digital converter portion receivingthe difference signal, and comprising a second modulator configured togenerate a fine analog to digital converter output, and a digitalcombiner, configured to combine the coarse analog to digital converteroutput and the fine analog to digital converter output, into a combineddigital output.
 2. The subranging superconducting analog to digitalconverter according to claim 1, wherein the fine analog to digitalconverter comprises a second delta modulator configured to generate asecond single bit stream of oversampled digital data, which is fed to asecond digital integrator and a second digital filter to produce thefine analog to digital converter output.
 3. The subrangingsuperconducting analog to digital converter according to claim 1,wherein the fine analog to digital converter comprises a delta-sigmamodulator and a digital filter configured to produce the fine analog todigital converter output.
 4. The subranging superconducting analog todigital converter according to claim 1, wherein the digital combinercombines the coarse analog to digital converter output and the fineanalog to digital converter output according to a weighting dependent onthe apportionment ratio.
 5. The subranging superconducting analog todigital converter according to claim 1, further comprising an analogdelay configured to delay the second portion before the analogsubtractor, wherein the at least one delay of the inter-range mixedsignal processor comprises a digitally adjustable digital delayconfigured to selectively delay the first single bit stream ofoversampled digital data from the coarse analog to digital converter independence on a digital delay parameter, the digital delay parameterbeing adjusted achieve a correct time alignment at the analogsubtractor.
 6. The subranging superconducting analog to digitalconverter according to claim 1, wherein the circuit of the inter-rangemixed signal processor further comprises a digital amplifier, an analogintegrator and analog filter configured to generate the second analogsignal from time delayed first single bit oversampled digital data. 7.The subranging superconducting analog to digital converter according toclaim 6, wherein the digital amplifier comprises an array of single fluxquantized digital gates configured to produce additive outputs.
 8. Thesubranging superconducting analog to digital converter according toclaim 6, wherein the digital amplifier comprises a network of activeJosephson transmission line splitters.
 9. The subranging superconductinganalog to digital converter according to claim 1, wherein the circuit ofthe inter-range mixed signal processor further comprises a fluxonamplifier, an analog integrator and analog filter configured to generatethe second analog signal from time delayed first single bit oversampleddigital data.
 10. The subranging superconducting analog to digitalconverter according to claim 1, wherein the coarse analog to digitalconverter portion comprises a phase modulation demodulation analog todigital converter, configured to receive the first portion and arepresentation of a carrier signal, wherein the fine analog to digitalconverter portion comprises a phase modulation demodulation analog todigital converter, configured to receive the difference signal and arepresentation of the carrier signal, and wherein the circuit of theinter-range mixed signal processor further comprises a differentialfluxon amplifier receiving the time delayed first single bit oversampleddigital data and a representation of the carrier signal, an analogintegrator and analog filter configured to generate the second analogsignal.
 11. The subranging superconducting analog to digital converteraccording to claim 1, wherein the coarse analog to digital converterportion comprises a phase modulation demodulation analog to digitalconverter, configured to receive the first portion and a representationof a carrier signal, wherein the fine analog to digital converterportion comprises a phase modulation demodulation analog to digitalconverter, configured to receive the difference signal and arepresentation of the carrier signal, wherein the inter-range mixedsignal processor further comprises a digital carrier subtractorconfigured to produce carrier-subtracted delayed single bit oversampleddigital data, and wherein the circuit of the inter-range mixed signalprocessor further comprises a differential fluxon amplifier receivingthe carrier-subtracted delayed single bit oversampled digital data, ananalog integrator and analog filter configured to generate the secondanalog signal.
 12. The subranging superconducting analog to digitalconverter according to claim 1, wherein the splitter comprises a fluxtransformer configured to inductively couple the first analog signal andthe second analog signal through two serially connected coils havingopposite polarity.
 13. The subranging superconducting analog to digitalconverter according to claim 12, wherein the splitter further comprisesthe flux transformer having a flux pump input for adding the carriersignal and offsetting the added carrier signal through a coil, furtherconfigured to act as an integrator.
 14. A method for converting ananalog signal to a digital signal, comprising: splitting a first analogsignal to provide a first portion and a second portion having anapportionment ratio; converting the first portion into a first singlebit stream of oversampled digital data with a coarse analog to digitalconverter comprising a first delta modulator configured to generate thefirst single bit stream of oversampled digital data, which is fed to afirst digital integrator and a first digital filter to produce a coarseanalog to digital converter output; receiving the first single bitstream of oversampled digital data and the second portion into aninter-range mixed signal processor; generating a second analog signalcorresponding to the single bit stream of oversampled digital data fromthe first delta modulator; time aligning the second portion and thesecond analog signal corresponding to the single bit stream ofoversampled digital data from the first delta modulator; subtracting thetime aligned second portion and the second analog signal with an analogsubtractor to produce a difference signal; converting the differencesignal into a digital signal with a fine analog to digital convertercomprising a second modulator configured to generate a fine analog todigital converter output, and digitally combining the coarse analog todigital converter output and the fine analog to digital converteroutput, into a combined digital output.
 15. The method according toclaim 14, further comprising combining the coarse analog to digitalconverter output and the fine analog to digital converter outputaccording to a weighting dependent on the apportionment ratio.
 16. Themethod according to claim 14, further comprising delaying the secondportion with an analog delay before the analog subtractor, wherein theat least one delay of the inter-range mixed signal processor comprises adigitally adjustable digital delay configured to selectively delay thefirst single bit stream of oversampled digital data from the coarseanalog to digital converter in dependence on a digital delay parameter,the digital delay parameter being adjusted to achieve a correct timealignment at the analog subtractor.
 17. The method according to claim14, further comprising digitally amplifying the first single bit streamof oversampled digital data in the inter-range mixed signal processor toproduce the second analog signal.
 18. The method according to claim 17,wherein said digitally amplifying comprises producing additive outputsfrom an array of single flux quantum digital gates.
 19. The methodaccording to claim 17, wherein said digitally amplifying comprisesproviding a differential fluxon amplifier receiving the first single bitstream of oversampled digital data and a carrier signal, and the coarseanalog to digital converter and the fine analog to digital convertereach comprise a phase modulation demodulation analog to digitalconverter.
 20. A method of signal processing, comprising: producing afirst stream of quantized pulses which represent an amplitude of areceived first analog signal with respect to the analog signal with afirst electronic circuit, delayed according to a digital controlparameter, to produce a first delayed digital stream; converting thefirst delayed digital stream into a second analog signal with a circuitcomprising at least one integrator; selectively producing an analogresidue signal representing a difference between an amplitude of thesecond analog signal and a delayed representation of the first analogsignal; controlling the digital control parameter to time-align thesecond analog signal with the delayed representation of the first analogsignal; producing a second stream of quantized pulses from the analogresidue signal; and combining the first stream of quantized pulses andthe second stream of quantized pulses into a composite digital signalrepresenting an amplitude of the first analog signal.